library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity memToReg is
  
  port (
    sel    : in  std_logic_vector(1 downto 0);
    in1    : in  std_logic_vector(31 downto 0);
    in2    : in  std_logic_vector(31 downto 0);
    in3    : in  std_logic_vector(31 downto 0);
    in4    : in  std_logic_vector(31 downto 0);
    result : out std_logic_vector(31 downto 0));
end memToReg;

architecture arch of memToReg is

begin  -- arch

  with sel select
    result <=
    in1 when "00" ,
    in2 when "01",
    in3 when "10",
    in4 when others;

end arch;
